1 tm march 1997 hm-6642 512 x 8 cmos prom features ? low power standby and operating power - iccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 a - iccop . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma at 1mhz ? fast access time . . . . . . . . . . . . . . . . . . . . . 120/200ns ? industry standard pinout ? single 5.0v supply ? cmos/ttl compatible inputs ? field programmable ? synchronous operation ? on-chip address latches ? separate output enable description the hm-6642 is a 512 x 8 cmos nicr fusible link programmable read only memory in the popular 24 pin, byte wide pinout. synchronous circuit design techniques combine with cmos processing to give this device high speed performance with very low power dissipation. on-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085. the output enable controls, both active low and active high, further simplify microprocessor system interfacing by allowing output data bus control independent of the chip enable control. the data output latches allow the use of the hm-6642 in high speed pipelined architecture systems, and also in synchronous logic replacement functions. applications for the hm-6642 cmos prom include low power handheld microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchro- nous logic replacement. all bits are manufactured storing a logical ?0? and can be selectively programmed for a logical ?1? at any bit location. ordering information package temperature range 120ns 200ns pkg. no. sbdip -40 o c to +85 o c hm1-6642b-9 hm1-6642-9 d24.6 smd# -55 o c to +125 o c 5962-8869002ja 5962-8869001ja d24.6 slim sbdip -40 o c to +85 o c HM6-6642B-9 hm6-6642-9 d24.3 smd# -55 o c to +125 o c 5962-8869002la 5962-8869001la d24.3 clcc -40 o c to +85 o c - hm4-6642-9 j28.a smd# -55 o c to +125 o c 5962-88690023a 5962-88690013a j28.a file number 3012.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2001. all rights reserved
2 functional diagram pinouts hm-6642 (sbdip) top view hm-6642 (clcc) top view 1 2 3 4 5 6 7 8 9 10 11 12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 16 17 18 19 20 21 22 23 24 15 14 13 v cc g1 g2 g3 e q7 q5 q4 q3 a8 p q6 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 a4 a3 a2 a1 a0 nc q0 g2 g3 e p nc q7 q6 q1 q2 gnd nc q3 q5 q4 a5 a6 a7 nc v cc g1 a8 pin description pin description nc no connect a0-a8 address inputs e chip enable q data output v cc power (+5v) g1 , g2 , g3 output enable p (note) program enable note: p should be hardwired to gnd except during programming. 8 8 8 8 8 8 64 x 64 matrix 64 6 e latched register address 6 3 a 3 a a3 a4 a5 a6 a7 a8 a0 a1 a2 8 8 a a d gated column decoder q0 q1 q2 q3 q4 q5 q6 q7 latched address register gated row decoder 8-bit data latch address latches and gated decoders: gate on falling edge of e latch on falling edge of e all lines positive logic - active high a high data latches: q latches on rising edge of e l high three state buffers: p should be hardwired to gnd except during programming g1 g2 g3 q = d output active hm-6642
3 programming introduction the hm-6642 is a 512 word by 8-bit field programmable read only memory utilizing nicrome fusible links as pro- grammable memory elements. selected memory locations are permanently changed from their manufactured state, of all low (v ol ) to a logical high (v oh ), by the controlled application of programming potentials and pulses. careful adherence to the following programming specifications will result in high programming yield. both high v cc (6.0v) and low v cc (4.0v) verify cycles are specified to assure the integrity of the programmed fuse. this programming specification, although complete, does not preclude rapid programming. the worst case programming time required is 37.4 seconds, and typical programming time can be approximately 4 seconds per device. the chip (e ) and output enable (g ) are used during the programming procedure. on proms which have more than one output enable control g3 is to be used. the other output enables must be held in the active, or enabled, state throughout the entire programming sequence. the program- mer designer is advised that all pins of the programmer?s socket should be at ground potential when the prom is inserted into the socket. v cc must be applied to the prom before any input or output pin is allowed to rise (see note). overall programming procedure 1. the address of the first bit to be programmed is presented, and latched by the chip enable (e ) falling edge. the output is disabled by taking the output enable g low: the programming pin is enabled by taking (p) high. 2. v cc is raised to the programming voltage level, 12.5v. 3. all data output pins are pulled up to v cc program. then the data output pin corresponding to the bit to be programmed is pulled low for 100ms. only one bit should be programmed at a time. 4. the data output pin is returned to v cc , and the v cc pin is returned to 6.0v. 5. the address of the bit is again presented, and latched by a second chip enable falling edge. 6. the data outputs are enabled, and read, to verify that the bit was successfully programmed. a). if verified, the next bit to be programmed is addressed and programmed. b). if not verified, the programs verify sequence is repeated up to 8 times total. 7. after all bits to be programmed have been verified at 6.0v, the v cc is lowered to 4.0v and all bits are verified. a). if all bits verify, the device is properly programmed. b). if any bit fails to verify, the device is rejected. programming system requirements 1. the power supply for the device to be programmed must be able to be set to three voltages: 4.0v, 6.0v, 12.5v. this supply must be able to supply 500ma average, and 1a dynamic, currents to the prom during programming. the power supply rise fall times when switching between voltages must be no quicker than 1ms. 2. the address drivers must be able to supply a v ih of 4.0v and 6.0v and v il when the system is at programming voltages. (see note) 3. the control input buffers must be able to maintain input voltage levels of 70% and 20% v cc for v ih and v il levels, respectively. notice that chip enable (e ) and g does not require a pull up to programming voltage levels. the program control (p) must switch from ground to vih and from v ih to the v cc pgm level. (see note) 4. the data input buffers must be able to sink up to 3ma from the prom?s output pins without rising more than 0.7v above ground, be able to hold the other outputs high with a current source capability of 0.5ma to 2.0ma, and not interfere with the reading and verifying of the data output of the prom. notice that a bit to be programmed is changed from a low state (v ol ) to high (v oh ) by pulling low on the output pin. a suggested implementation is open collector ttl buffers (or inverters) with 4.7k ? pull up resistors to v cc . (see note) note: never allow any input or output pin to rise more than 0.3v above v cc , or fall more than 0.3v below ground. hm-6642
4 background information hm-6642 programming programming specifications symbol parameter limits units min typ max vcc prog programming vcc 12.0 12.0 12.5 v vccn operating vcc 4.5 5.5 5.5 v vcc lv special verify vcc 4.0 - 6.0 v icc system icc capability 500 - - ma icc peak transient icc capability 1.0 - - a prom input pins vol output low voltage (to prom) -0.3 gnd 20% vcc v voh output high voltage (to prom) 70% vcc vcc vcc +0.3 v iol output sink current (at vol) 0.01 - - ma ioh output source current (at voh) 0.01 - - ma prom data output pins vol output low voltage (to prom) -0.3 gnd 0.7 v voh output high voltage (to prom) 70% vcc vcc vcc +0.3 v iol output sink current (at vol) 3.0 - - ma ioh output source current (at voh) 0.5 1.0 2.0 ma td delay time 1.0 1.0 - s tr rise time 1.0 10.0 10.0 s tf fall time 1.0 10.0 10.0 s tehel chip enable pulse width 500 - - ns tavel address valid to chip enable low time 500 - - ns telqv chip enable low to output valid time - - 500 ns tpw programming pulse width 90 100 110 s tip input leakage at vcc = vcc prog -10 +1.0 10 a ta ambient temperature - 25 - o c hm-6642
5 figure 1. hm-6642 programming cycle figure 2. hm-6642 post programming verify cycle tehel td verify valid programming valid td td td td tr td td tf tpw read data vcc prog vih vil vih vil v cc prog vih vil v cc prog vih vil v cc prog vcc gnd v cc prog vih/voh vil/vol a e g p v cc q valid tavel tehel tehel vih vil vih vil 6.0v 5.0v 4.0v 0.0v voh vol telqv read telqv read read telqv tehel td td a e v cc q hm-6642
6 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.3v to v cc +0.3v typical derating factor . . . . . . . . . . . 5ma/mhz increase in iccop esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range hm-6642b-9, hm-6642-9 . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c thermal resistance ja jc sbdip package. . . . . . . . . . . . . . . . . . 52 o c/w 14 o c/w slim sbdip . . . . . . . . . . . . . . . . . . . . . 70 o c/w 19 o c/w clcc package . . . . . . . . . . . . . . . . . . 58 o c/w 14 o c/w maximum storage temperature range . . . . . . . . .-65 o c to +150 o c maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . +175 o c maximum lead temperature (soldering 10s)+300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. dc electrical specifications v cc = 5v 10%; t a = -40 o c to +85 o c (hm-6642b-9, hm-6642-9) symbol parameter limits units test conditions min max iccsb standby supply current - 100 a io = 0, vi = vcc or gnd, vcc = 5.5v iccop operating supply current (note 3) - 20 ma f = 1mhz, io = 0, vi = vcc or gnd, vcc = 5.5v ii input leakage current -1.0 +1.0 agnd vi vcc, vcc = 5.5v ioz output leakage current -1.0 +1.0 agnd vo vcc, vcc = 5.5v vil input low voltage -0.3 0.8 v vcc = 4.5v vih input high voltage 2.4 vcc + 0.3 v vcc = 5.5v vol output low voltage - 0.4 v iol = 3.2ma, vcc = 4.5v voh1 output high voltage 2.4 - v ioh = -1.0ma, vcc = 4.5v voh2 output high voltage (note 2) vcc - 1.0 - v ioh = -100 a, vcc = 4.5v ac electrical specifications symbol parameter limits units test conditions hm-6642b-9 hm-6642-9 min max min max (1) telqv chip enable access time - 120 - 200 ns notes 1, 4 (2) tavqv address access time (tavqv = telqv + tavel) -140-220ns notes 1, 4 (3) tgvqv output enable access time - 50 - 150 ns notes 1, 4 (4) tgvqx output enable time 5 50 5 150 ns notes 2, 4 (5) tgxqz output disable time - 50 - 150 ns notes 2, 4 (6) teleh chip enable pulse negative width 120 - 200 - ns notes 1, 4 (7) telel read cycle time 160 - 350 - ns notes 1, 4 (8) tehel chip enable pulse positive width 40 - 150 - ns notes 1, 4 (9) tavel address setup time 20 - 20 - ns notes 1, 4 (10) telax address hold time 25 - 60 - ns notes 1, 4 hm-6642
7 test load circuit capacitance t a = +25 o c symbol parameter limits units test conditions min max ci input capacitance (note 2) - 10.0 pf f = 1mhz, all measurements reference device ground co output capacitance (note 2) - 12.0 pf notes: 1. input pulse levels: 0 to 3.0v; input rise and fall times: 5ns (max); input and output timing reference level: 1.5v; output load: 1 ttl gate equivalent c l = 50pf (min) - for c l greater than 50pf, access time is derated by 0.15ns per pf. 2. tested at initial design and after major design changes. 3. typical derating 5ma/mhz increase in iccop. 4. v cc = 4.5v and 5.5v. switching waveform note: g has the same timing as g except signal is inverted. figure 3. read cycle tgxqz (5) tehel (8) tavel (9) telel (7) teleh telqv tgvqv tgvqx (2) telax (9) tehel tgxqz a e q g time (note) reference tavel tavqv (10) (5) (8) add valid (3) (4) (1) (6) data valid next add -1 0 1 2 3 456 dut equivalent circuit 1.5v iol ioh c l note: capacitance, includes stray and jig capacitance (note) test head hm-6642
8 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 hm-6642
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